In order to control and/or synchronize operations in an electronic circuit, a clock signal may be used. The clock signal may e.g. be generated externally outside of a semiconductor chip comprising the electronic circuit or parts thereof, e.g. by means of a crystal oscillator. As another example, the clock signal may be generated internally on the chip, e.g. by means of a phase-locked loop (PLL).
Some circuits may require a clock signal with a relatively well-defined or controlled duty cycle, i.e. the relative portion of a clock cycle during which the clock signal is high. As a nonlimiting example, a resettable comparator circuit may be used e.g. in an analog-to-digital converter (ADC). The comparator circuit may e.g. be arranged to compare an input voltage of the ADC, or a voltage derived therefrom, with a reference voltage of the ADC. The comparator circuit may be arranged to be reset between consecutive comparisons. The clock signal may be used to control the operation of the comparator circuit. For example, the comparator circuit may be arranged to be reset during a “high” state of the clock signal (i.e. corresponding to a logic ‘1’) and to be operative to perform a comparison during a “low” state of the reset signal (i.e. corresponding to a logic ‘0’).
In order for the comparator to be properly reset, a certain amount of reset time may be needed. On the other hand, in order to perform a comparison and output a correct result, a certain amount of comparison time may be needed. If the reset time is too short, the result of the subsequent comparison may be influenced not only by the input voltages to the comparator, but also by previous comparisons. Furthermore, the input voltages to the comparator might not be given enough time to settle before the subsequent comparison is to be performed. On the other hand, if the comparison time is to short, the comparator may not be able to make a decision, especially if the difference between the input voltages is relatively small. For such a comparator circuit, there may be an optimum or near-optimum trade-off between reset time and comparison time, which translates to an optimum or near optimum duty cycle for the clock signal.
The duty cycle of a clock signal generated externally or internally, e.g. by means of a crystal oscillator, PLL, or the like, may have a different duty cycle than the desired duty cycle. Alternatively or additionally, the duty cycle may vary between chips and/or in time, e.g. due to temperature variations and aging of components.
Hence, there is a need for means for generating a clock signal with a well-defined or controlled duty cycle.